Skip to main content

Enabling Programmable Transport Protocols in High-Speed NICs

Author(s): Arashloo, Mina T; Lavrov, Alexey; Ghobadi, Manya; Rexford, Jennifer; Walker, David; et al

To refer to this page use:
Abstract: Data-center network stacks are moving into hardware to achieve 100 Gbps data rates and beyond at low latency and low CPU utilization. However, hardwiring the network stack in the NIC would stifle innovation in transport protocols. In this paper, we enable programmable transport protocols in high-speed NICs by designing Tonic, a flexible hardware architecture for transport logic. At 100 Gbps, transport protocols must generate a data segment every few nanoseconds using only a few kilobits of per-flow state on the NIC. By identifying common patterns across transport logic of different transport protocols, we design an efficient hardware "template" for transport logic that satisfies these constraints while being programmable with a simple API. Experiments with our FPGA-based prototype show that Tonic can support the transport logic of a wide range of protocols and meet timing for 100 Gbps of back-to-back 128-byte packets. That is, every 10 ns, our prototype generates the address of a data segment for one of more than a thousand active flows for a downstream DMA pipeline to fetch and transmit a packet.
Publication Date: 2020
Citation: Arashloo, Mina Tahmasbi, Alexey Lavrov, Manya Ghobadi, Jennifer Rexford, David Walker, and David Wentzlaff. "Enabling Programmable Transport Protocols in High-Speed NICs." In 17th USENIX Symposium on Networked Systems Design and Implementation (2020): pp. 93-109.
Pages: 93 - 109
Type of Material: Conference Article
Journal/Proceeding Title: 17th USENIX Symposium on Networked Systems Design and Implementation
Version: Final published version. This is an open access article.

Items in OAR@Princeton are protected by copyright, with all rights reserved, unless otherwise indicated.