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CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework

Author(s): Tuli, Shikhar; Li, Chia-Hao; Sharma, Ritvik; Jha, Niraj K

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dc.contributor.authorTuli, Shikhar-
dc.contributor.authorLi, Chia-Hao-
dc.contributor.authorSharma, Ritvik-
dc.contributor.authorJha, Niraj K-
dc.identifier.citationTuli, Shikhar, Li, Chia-Hao, Sharma, Ritvik, Jha, Niraj K. (2022). CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework. ACM Transactions on Embedded Computing Systems, 10.1145/3575798en_US
dc.description.abstractRecently, automated co-design of machine learning (ML) models and accelerator architectures has attracted significant attention from both the industry and academia. However, most co-design frameworks either explore a limited search space or employ suboptimal exploration techniques for simultaneous design decision investigations of the ML model and the accelerator. Furthermore, training the ML model and simulating the accelerator performance is computationally expensive. To address these limitations, this work proposes a novel neural architecture and hardware accelerator co-design framework, called CODEBench. It comprises two new benchmarking sub-frameworks, CNNBench and AccelBench, which explore expanded design spaces of convolutional neural networks (CNNs) and CNN accelerators. CNNBench leverages an advanced search technique, BOSHNAS, to efficiently train a neural heteroscedastic surrogate model to converge to an optimal CNN architecture by employing second-order gradients. AccelBench performs cycle-accurate simulations for diverse accelerator architectures in a vast design space. With the proposed co-design method, called BOSHCODE, our best CNN-accelerator pair achieves 1.4% higher accuracy on the CIFAR-10 dataset compared to the state-of-the-art pair while enabling 59.1% lower latency and 60.8% lower energy consumption. On the ImageNet dataset, it achieves 3.7% higher Top1 accuracy at 43.8% lower latency and 11.2% lower energy consumption. CODEBench outperforms the state-of-the-art framework, i.e., Auto-NBA, by achieving 1.5% higher accuracy and 34.7× higher throughput while enabling 11.0× lower energy-delay product (EDP) and 4.0× lower chip area on CIFAR-10.en_US
dc.relation.ispartofACM Transactions on Embedded Computing Systemsen_US
dc.rightsAuthor's manuscripten_US
dc.titleCODEBench: A Neural Architecture and Hardware Accelerator Co-Design Frameworken_US
dc.typeJournal Articleen_US

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