Skip to main content

FinFETs: From Devices to Architectures

Author(s): Bhattacharya, D; Jha, NK

To refer to this page use:
Abstract: Since Moore’s law driven scaling of planar MOSFETs faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing to the presence of multiple (two/three) gates, FinFETs/Trigate FETs are able to tackle short-channel effects (SCEs) better than conventional planar MOSFETs at deeply scaled technology nodes and thus enable continued transistor scaling. In this paper, we review research on FinFETs from the bottommost device level to the topmost architecture level. We survey different types of FinFETs, various possible FinFET asymmetries and their impact, and novel logic-level and architecture-level tradeoffs offered by FinFETs. We also review analysis and optimization tools that are available for characterizing FinFET devices, circuits, and architectures.
Publication Date: 5-Aug-2015
Citation: Bhattacharya, D, Jha, NK. (2015). FinFETs: From devices to architectures. ? - ? (21-55). doi:10.1017/CBO9781316156148.003
DOI: doi:10.1017/CBO9781316156148.003
Type of Material: Journal Article
Version: Author's manuscript

Items in OAR@Princeton are protected by copyright, with all rights reserved, unless otherwise indicated.