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Verifying Correct Microarchitectural Enforcement of Memory Consistency Models

Author(s): Lustig, D; Pellauer, M; Martonosi, Margaret

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dc.contributor.authorLustig, D-
dc.contributor.authorPellauer, M-
dc.contributor.authorMartonosi, Margaret-
dc.date.accessioned2021-10-08T19:45:30Z-
dc.date.available2021-10-08T19:45:30Z-
dc.date.issued2015en_US
dc.identifier.citationLustig, D, Pellauer, M, Martonosi, M. (2015). Verifying Correct Microarchitectural Enforcement of Memory Consistency Models. IEEE Micro, 35 (72 - 82. doi:10.1109/MM.2015.47en_US
dc.identifier.urihttp://arks.princeton.edu/ark:/88435/pr13c2r-
dc.description.abstractMemory consistency models define the rules and guarantees about the ordering and visibility of memory references on multithreaded CPUs and systems on chip. PipeCheck offers a methodology and automated tool for verifying that a particular microarchitecture correctly implements the consistency model required by its architectural specification.en_US
dc.format.extent72 - 82en_US
dc.language.isoen_USen_US
dc.relation.ispartofIEEE Microen_US
dc.rightsAuthor's manuscripten_US
dc.titleVerifying Correct Microarchitectural Enforcement of Memory Consistency Modelsen_US
dc.typeJournal Articleen_US
dc.identifier.doidoi:10.1109/MM.2015.47-
pu.type.symplectichttp://www.symplectic.co.uk/publications/atom-terms/1.0/journal-articleen_US

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