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Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification

Author(s): Huang, Boyuan; Zhang, Hongce; Subramanyan, Pramod; Vizel, Yakir; Gupta, Aarti; et al

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dc.contributor.authorHuang, Boyuan-
dc.contributor.authorZhang, Hongce-
dc.contributor.authorSubramanyan, Pramod-
dc.contributor.authorVizel, Yakir-
dc.contributor.authorGupta, Aarti-
dc.contributor.authorMalik, Sharad-
dc.date.accessioned2021-10-08T19:46:40Z-
dc.date.available2021-10-08T19:46:40Z-
dc.date.issued2018-12en_US
dc.identifier.citationHuang, Bo-Yuan, Hongce Zhang, Pramod Subramanyan, Yakir Vizel, Aarti Gupta, and Sharad Malik. "Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification." ACM Transactions on Design Automation of Electronic Systems 24, no. 1 (2018): pp. 10:1-10:24. doi:10.1145/3282444en_US
dc.identifier.issn1084-4309-
dc.identifier.urihttps://arxiv.org/pdf/1801.01114.pdf-
dc.identifier.urihttp://arks.princeton.edu/ark:/88435/pr10r8c-
dc.description.abstractModern Systems-on-Chip (SoC) designs are increasingly heterogeneous and contain specialized semi-programmable accelerators in addition to programmable processors. In contrast to the pre-accelerator era, when the ISA played an important role in verification by enabling a clean separation of concerns between software and hardware, verification of these “accelerator-rich” SoCs presents new challenges. From the perspective of hardware designers, there is a lack of a common framework for formal functional specification of accelerator behavior. From the perspective of software developers, there exists no unified framework for reasoning about software/hardware interactions of programs that interact with accelerators. This article addresses these challenges by providing a formal specification and high-level abstraction for accelerator functional behavior. It formalizes the concept of an Instruction Level Abstraction (ILA), developed informally in our previous work, and shows its application in modeling and verification of accelerators. This formal ILA extends the familiar notion of instructions to accelerators and provides a uniform, modular, and hierarchical abstraction for modeling software-visible behavior of both accelerators and programmable processors. We demonstrate the applicability of the ILA through several case studies of accelerators (for image processing, machine learning, and cryptography), and a general-purpose processor (RISC-V). We show how the ILA model facilitates equivalence checking between two ILAs, and between an ILA and its hardware finite-state machine (FSM) implementation. Further, this equivalence checking supports accelerator upgrades using the notion of ILA compatibility, similar to processor upgrades using ISA compatibility.en_US
dc.format.extent10:1 - 10:24en_US
dc.language.isoen_USen_US
dc.relation.ispartofACM Transactions on Design Automation of Electronic Systemsen_US
dc.rightsAuthor's manuscripten_US
dc.titleInstruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verificationen_US
dc.typeJournal Articleen_US
dc.identifier.doi10.1145/3282444-
dc.identifier.eissn1557-7309-
pu.type.symplectichttp://www.symplectic.co.uk/publications/atom-terms/1.0/journal-articleen_US

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