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PipeCheck: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models

Author(s): Lustig, Daniel; Pellauer, Michael; Martonosi, Margaret

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Abstract: We present PipeCheck, a methodology and automated tool for verifying that a particular micro architecture correctly implements the consistency model required by its architectural specification. PipeCheck adapts the notion of a "happens before" graph from architecture-level analysis techniques to the micro architecture space. Each node in the "micro architecturally happens before" (μhb) graph represents not only a memory instruction, but also a particular location (e.g., Pipeline stage) within the micro architecture. Architectural specifications such as "preserved program order" are then treated as propositions to be verified, rather than simply as assumptions. PipeCheck allows an architect to easily and rigorously test whether a micro architecture is stronger than, equal in strength to, or weaker than its architecturally-specified consistency model. We also specify and analyze the behavior of common micro architectural optimizations such as speculative load reordering which technically violate formal architecture-level definitions. We evaluate PipeCheck using a library of established litmus tests on a set of open-source pipelines. Using PipeCheck, we were able to validate the largest pipeline, the Open SPARC T2, in just minutes. We also identified a bug in the O3 pipeline of the gem5 simulator.
Publication Date: 2014
Citation: Lustig, Daniel, Michael Pellauer, and Margaret Martonosi. "PipeCheck: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models." 47th Annual IEEE/ACM International Symposium on Microarchitecture (2014): pp. 635-646. doi:10.1109/MICRO.2014.38
DOI: 10.1109/MICRO.2014.38
ISSN: 1072-4451
EISSN: 2379-3155
Pages: 635 - 646
Type of Material: Conference Article
Journal/Proceeding Title: 47th Annual IEEE/ACM International Symposium on Microarchitecture
Version: Author's manuscript

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