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Loop Summarization with Rational Vector Addition Systems

Author(s): Silverman, Jake; Kincaid, Zachary

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dc.contributor.authorSilverman, Jake-
dc.contributor.authorKincaid, Zachary-
dc.date.accessioned2021-10-08T19:45:09Z-
dc.date.available2021-10-08T19:45:09Z-
dc.date.issued2019en_US
dc.identifier.citationSilverman, Jake, and Zachary Kincaid. "Loop Summarization with Rational Vector Addition Systems." In International Conference on Computer Aided Verification (2019): pp. 97-115. doi:10.1007/978-3-030-25543-5_7en_US
dc.identifier.issn0302-9743-
dc.identifier.urihttp://arks.princeton.edu/ark:/88435/pr1cz3c-
dc.description.abstractThis paper presents a technique for computing numerical loop summaries. The method synthesizes a rational vector addition system with resets ( ℚ -VASR) that simulates the action of an input loop, and then uses the reachability relation of that ℚ -VASR to over-approximate the behavior of the loop. The key technical problem solved in this paper is to automatically synthesize a ℚ -VASR that is a best abstraction of a given loop in the sense that (1) it simulates the loop and (2) it is simulated by any other ℚ -VASR that simulates the loop. Since our loop summarization scheme is based on computing the exact reachability relation of a best abstraction of a loop, we can make theoretical guarantees about its behavior. Moreover, we show experimentally that the technique is precise and performant in practice.en_US
dc.format.extent97 - 115en_US
dc.language.isoen_USen_US
dc.relation.ispartofInternational Conference on Computer Aided Verificationen_US
dc.rightsFinal published version. Article is made available in OAR by the publisher's permission or policy.en_US
dc.titleLoop Summarization with Rational Vector Addition Systemsen_US
dc.typeConference Articleen_US
dc.identifier.doi10.1007/978-3-030-25543-5_7-
pu.type.symplectichttp://www.symplectic.co.uk/publications/atom-terms/1.0/conference-proceedingen_US

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